1. Field of the Invention
The present invention relates generally to integrated circuit packaging, and in particular to flip-chip and wire bond ball grid array (BGA) integrated circuit packages. Still more particularly, the present invention relates to forming a low stress and low profile cavity down flip chip and wire bond BGA package.
2. Description of the Related Art
Integrated circuit packaging technology is becoming a somewhat limiting factor in development of higher performance, packaged integrated circuits. Package designers are struggling to keep pace with the increase in pin count, size limitations, low profile mounting constraints, and other evolving requirements for packaging and mounting integrated circuits. One common packaging and package mounting solution currently being utilized is a ball grid array (BGA) package, in which an array of selective solderable areas for solder balls (or xe2x80x9cbumpsxe2x80x9d) are formed on the integrated circuit package. Conductive leads or traces on the package connect the selective solderable areas to wire bond sites for wire bonds connecting to the integrated circuit die within the package. A corresponding array of selective solderable areas are formed on a printed circuit board (PCB) substrate on which the packaged integrated circuit is to be mounted and connect, with conductive traces or leads, to other discrete or integrated circuit devices or to connector pins or edge connectors on the printed circuit board. Solder balls or bumps are formed on the selective solderable areas in the grid array of either the package or the PCB substrate, placed over the corresponding selective solderable areas in the other grid array, and then heated to a temperature sufficient to melt the solder balls and solder the package to the PCB substrate.
Within the integrated circuit package, the integrated circuit die is placed on a package substrate or within a cavity in a die carrier (which often also serves a heat sink or heat spreader). Wire bonds are formed connecting bonds pads on the integrated circuit die to corresponding nearby wire bond sites on the package substrate or die carrier, which are connected in turn by conductive traces or leads to selective solderable areas for solder bumps. The selective solderable areas on the package substrate or die carrier may be either on the same major surface of the package substrate or die carrier as the cavity and/or integrated circuit die, for mounting the packaged integrated circuit xe2x80x9ccavity downxe2x80x9d on the PCB substrate, or on the opposite major surface (or xe2x80x9csidexe2x80x9d) from the cavity, for mounting the packaged integrated circuit xe2x80x9ccavity upxe2x80x9d on the PCB substrate. When the selective solderable areas on the die carrier are located on the opposite side of the package substrate die carrier from the die cavity, the conductive traces connecting the selective solderable areas to the wire bond sites near the cavity may pass through the package substrate or die carrier or around one or more edges of the package substrate or die carrier.
FIG. 1 illustrates a thin fine-pitch BGA (TFBGA) wire bond package 102 which, with respect to the present invention, represents a relatively early stage in the evolution of BGA packages. TFBGA package 102 includes a multilayer printed circuit board (PCB) substrate 104 having a first layer 106 of conductive traces and a second layer 108 of conductive traces on opposite sides of and separated by one or more insulating layer(s) 110. Plated through holes 112 are arranged throughout multilayer PCB substrate 104 to electrically connect wire bonding sites 106a-106n in the first layer 106 to conductive traces in the second layer 108, with bonding wires 114 extending between wire bonding sites 116 and corresponding bond pads 118 arranged upon the integrated circuit die 120. Integrated circuit die 120 is held in place upon PCB substrate 104 by a layer of adhesive 122, typically silver epoxy glue, and integrated circuit die 120, adhesive 122, bonding wires 114, wire bonding sites 116, and bond pads 118 are all enclosed by an encapsulating cap 124, such as a hardened plastic resin. By conventional solder-bumping and reflow processes, a plurality of solder balls 126 are arranged in a grid array on the opposite side of PCB substrate 104 from integrated circuit die 120 and attached to conductive traces 108. Solder balls 126 are then electrically connected to a solder ball attachment sites 128 on a main PCB 130, which may be any of a large variety of integrated circuit cards such as motherboards, adapter cards, and the like. TFBGA package 102 is typically about 1.15 millimeters (mm) thick, although the thickness may range from about 1.07 mm to about 1.23 mm.
FIG. 2 illustrates an ultra fine-pitch BGA (UFBGA) wire bonded package 202, the successor to TFBGA package 102 in the evolution of BGA packages. UFBGA package 202 includes a single-layer printed circuit board (PCB) substrate 204 having a metal tape layer 206 and plated through holes 208 arranged throughout PCB substrate 204 to electrically connect wire bonding sites 210 on an upper surface of PCB substrate 204 to conductive traces 212 on a lower surface of PCB substrate 204. Bonding wires 214 extend between and connect wire bonding sites 210 and bond pads 216 on the integrated circuit die 218. The remaining features of UFBGA package 202 parallel corresponding features of TFBGA package 102 in FIG. 1, except UFBGA package 202 is typically only about 0.93 mm thick, and generally no less than about 0.86 mm and no more than about 1.00 mm in thickness. This package style is thinner than TFBGA and is the preferred design for miniaturization.
Solder balls or bumps may also be employed in arrays in mounting integrated circuit die (or xe2x80x9cchipsxe2x80x9d) to the die carrier for thin packages. Bumped silicon chips, often referred to as xe2x80x9cflip-chipsxe2x80x9d since they are mounted with the active layer side of the die adjacent to the die carrier rather than the backside, use a solder bump or ball to solder the electrical connections that interconnect integrated circuits within the die to conductive leads on the die carrier. Solder bumps or balls allow direct coupling between the pads on the silicon chip in which the integrated circuit is formed and matching contacts on the die carrier or package substrate. The flip-chip is aligned to the die carrier or package substrate and all connections are made simultaneously by reflowing the solder. A polymer underfill within the gap between the silicon chip and the package substrate is formed following reflow of the solder bumps to increase the mechanical integrity and reliability of integrated circuit packages.
FIG. 3 illustrates a thin fine-pitch BGA (TFBGA) flip-chip package 302, which followed and overlapped TFBGA and UFBGA wire bond packages in the evolution of BGA packages. Flip chip package 302 includes a single-layer printed circuit board (PCB) substrate 304, typically copper plated on both sides to receive solder balls 306 on conductive traces 308 disposed upon a lower surface 310 as well as smaller solder balls 312 at bonding sites 314 on an upper surface 316 of PCB substrate 304. Solder balls 306 and small solder balls 312 are arranged in a grid array and attached to conductive traces 308 and bonding sites 314 by conventional solder-bumping and reflow processes.
In flip-chip package 302, an integrated circuit die 318 is xe2x80x9cinvertedxe2x80x9d and electrically connected at the surface of an xe2x80x9cupperxe2x80x9d or active layer to PCB substrate 304 via small solder balls 312 as described above. Afterwards an underfill material 320, typically epoxy, is disposed in all of the void space between integrated circuit die 318 and PCB substrate 304. Solder balls 306 are then electrically connected to solder ball attachment sites 322 on main PCB 324. Thus, flip-chip package 302 does not require bonding wires, and has a total typical thickness of about 1.14 mm, or within the range of about 1.07 mm to about 1.21 mm in total package thickness.
FIGS. 4 and 5 illustrate variations of a cavity down high performance BGA (HBGA) wire bond package 402, 502, which includes a die carrier or package substrate 404, 504 having a central cavity 406, 506 in which an integrated circuit die 408, 508 is attached, by an adhesive substance, to an interior surface of cavity 406, 506. Bond wires 410, 510 between bond pads on integrated circuit die 408, 508 and wire bonding sites on an insulating tape layer which surrounds cavity 406, 506, together with solder balls 412, 512, arranged in a grid array and electrically connected both to conductive traces formed on the insulating tape layer and to a main PCB 414, 514 at solder ball attachment sites, provide electrical connection from the integrated circuit die 408, 508 through the cavity down package 402, 502 to the PCB 414, 514 on which the package 402, 502 is mounted.
Integrated circuit die 408, 508, bonding wires 410, 510, the bonding pads on integrated circuit die 408, 508, and wire bonding sites on the insulating tape layer are encapsulated by an encapsulation cap 416, 516 with a slight clearance (approximately 5 mils), as shown, between encapsulation cap 416, 516 and main PCB 414, 514. Because integrated circuit die 408, 508 is sunken within cavity 406, 508, cavity down package 402, 502 can have a reduced overall height, useful for small or thin profile devices such as wireless telephones or pagers, hand-held personal digital assistants, and the like.
The packaging configuration illustrated in FIG. 4 requires solder balls 412 to have a final, assembled height of about 19 mils, which corresponds to an initial solder ball height (prior to collapse during reflow) of about 24-25 mils and a center-to-center spacing (or xe2x80x9cgrid pitchxe2x80x9d) between adjacent solder balls of approximately 50 mils. In order to increase the xe2x80x9cpinxe2x80x9d count, or the number of connections between the packaged integrated circuit and the PCB substrate on which the packaged integrated circuit is to be mounted, without increasing the size of the major surfaces of the package, a finer pitch solder ball array is required. Decreasing the pitch of the solder balls requires a commensurate decrease in their size, which reduces the stand-off between the packaged integrated circuit and the PCB substrate on which the packaged integrated circuit is mounted.
To reduce the height of the mounted, cavity down HBGA wire bond integrated circuit package when moving to finer pitched solder balls, the required thickness for the encapsulation cap is reduced, as shown by encapsulation cap 516 in FIG. 5, by connecting wire bonds 510 from bond pads on the integrated circuit die 508 to wire bonding sites inside the cavity 506, on an insulating tape layer which surrounds and extends into cavity 506 to provide wire bonding sites on the interior surface of cavity 506, rather than to the surface of package substrate 504. The resulting thinner encapsulation cap allows smaller, finer pitched solder balls to be employed, since less stand-off is required, which in turn results in a lower mounted package height. However, both of these packages (FIGS. 4 and 5) are based on multilayer construction, such as laminating various flat pieces together.
Unlike wire bond BGA packages, flip-chip BGA packages are almost universally assembled and mounted with the die carrier cavity up on PCB substrates because the solder balls between the package and the PCB substrate are too low and the flip-chip integrated circuit die are too thick. Solder balls employed to mount a BGA package on a PCB substrate generally only provide about 19-20 mils (approximately 0.5 mm) in stand-off between the BGA packaged integrated circuit and the PCB substratexe2x80x94that is, the solder balls have a height of only about 20 mils after surface mount solder reflow. The integrated circuit die packaged within the BGA package are too thickxe2x80x94about 25-30 mils without back grindxe2x80x94to be successfully packaged in the BGA package and mounted cavity down on the PCB substrate with such a small amount of stand-off while remaining within target ranges for total-thickness or height of the mounted package.
Any BGA package that utilizes solder balls to conductively couple the packaged integrated circuit to a main PCB is susceptible to failure, particularly fatigue failure, due to temperature fluctuations and dissimilarity in thermal expansion rates for the components that form the BGA package. FIG. 6 illustrates, in an enlarged view of portion of a typical BGA package, the persistent problem of stress failure associated with all of the above varieties of BGA packages (wire bond or flip-chip, cavity up or cavity down). A cavity up wire bond BGA package 602 shown in FIG. 6 to be electrically connected to a main PCB 604 via solder balls 606 (which is selected as merely exemplary and may instead be a flip-chip, cavity down, or any other variant of BGA package that utilizes solder balls 606 to conductively couple BGA package 602 to a main PCB 604) includes a PCB substrate 608 to which is attached an integrated circuit die 610 via an adhesive layer 612. Bond wires 614 extend from conductive bond pads located on integrated circuit die 610 to wire bonding sites located upon PCB substrate 608, all of which are encapsulated, together with integrated circuit die 610, adhesive layer 612, and sealed together by an encapsulation cap 616.
BGA package 602 may be logically divided into three portions: a first portion 618a located beneath integrated circuit die 610; a second portion 618b enclosed within encapsulation cap 616, but not located beneath integrated circuit die 610; and a third portion 618c extending outward adjacent to encapsulation cap 616, which is not located beneath either integrated circuit die 610 or encapsulation cap 616. Although PCB substrate 608, integrated circuit die 610, adhesive layer 612, bonding wires 614, and encapsulation cap 616 each have separate and distinct coefficients of heat transfer and corresponding rates of thermal expansion, when these components are combined, as in first portion 618a, a single, xe2x80x9ceffectivexe2x80x9d coefficient of heat transfer (and a corresponding single, xe2x80x9ceffectivexe2x80x9d rate of thermal expansion) exists. Likewise, within second portion 618b, consisting of adhesive layer 612, bonding wires 614, and encapsulation cap 616, a single, xe2x80x9ceffectivexe2x80x9d coefficient of heat transfer and corresponding effective rate of thermal expansion is created, which will often differ from the effective rate of thermal expansion in first portion 618a and the effective rate of thermal expansion in third portion 618c. 
For example, integrated circuit die 610 is made primarily of silicon and has a thermal expansion rate of about 26 parts per million (ppm) per degree Centigradexe2x80x94that is, integrated circuit die 610 expands 26 inches per xc2x0 C. for every million inches along a particular dimension. On the other hand, PCB substrate 608 and main PCB 604 are typically made of fiber-glass or other non-conductive material and have thermal expansion rates of about 17 ppm/xc2x0 C. Thus, BGA package 602 includes at least three portions 618a, 618b, and 618c that have dissimilar thermal expansion rates. For this reason, as BGA package 602 cools from the solder reflow temperature or undergoes ambient temperature changes during use, BGA package experiences thermal contraction (or expansion) at different rates in different portions, thereby stressing and staining solder balls 606. Such stressed and strained condition is depicted by solder balls 606a and PCB substrate 608a shown in dashed lines in FIG. 6. This stressed and strained condition of solder balls 606a results in a high stress concentration. The dashed lines (606a and 608a) represent the position(s) of BGA package 602 and solder balls 606 at high temperature, such as during reflow of solder; the solid lines (606 and 608) represent the positions of the respective components at room temperature.
Furthermore, electrical current flowing through BGA package 602 during operation cause BGA package to cyclically or intermittently heat up and cool down, which causes additional thermal expansion and contraction, although probably considerably less than at reflow. But, because of the stressed and strained condition of solder balls 606a after cooling from the reflow process, the cyclical or intermittent heating and cooling of BGA package 602 during normal operation may lead to fatigue failure of BGA package 602. Thin profile packages are more susceptible than thicker packages to this problem due primarily to the lower standoff height of the smaller solder balls.
It would be desirable, therefore, to provide a low stress and low profile cavity down flip chip and/or wire bond BGA package in which fatigue-failure from dissimilar thermal expansion rates is alleviated.
A low stress, low profile, cavity down wire bond or flip-chip BGA package is formed by injection molding or thermosetting of liquid crystal plastic (LCP) to form a die carrier including a polymer solder grid array (PSGA) of standoff posts formed during molding of the die carrier. The standoff posts are coated with copper during plating of the die carrier, on the surfaces of which conductive traces are etched from the standoff posts into a die cavity to wire bond sites or small solderable areas at the bottom of the cavity. After mounting of a wire bond or flip-chip integrated circuit die within the die cavity of the die carrier, the packaged integrated circuit is mounted on a main printed circuit board (PCB) substrate utilizing epoxy paste and/or solder paste to conductively couple the standoff posts to conductive solderable areas on the main PCB substrate. The high aspect ratio and/or large height of the plated standoff posts reduces stress on the solder joints and, combined with the flexibility of the LCP die carrier, improves solder joint reliability after reflow and during operation.